The present invention relates generally to integration of high performance copper (Cu) inductors with bond pads, and more particularly pertains to integration of high performance copper inductors with global interconnects, and with either Al bond pads or Cu bond pads, where the Cu for the inductor and the global interconnects is defined by a resist pattern above the chip passivation layer. In addition, the inductor can be fabricated by superposing the adjacent wiring layers or levels to form a laminate inductor, with the metal levels being interconnected by a bar via.
Copper inductors are being used increasingly in RF integrated circuits. The performance of a Cu inductor is maximized by maximizing the thickness of the Cu. This can be achieved by plating a thick Cu layer (>5 um) inside a resist mask.
Unfortunately, it is difficult to passivate thick Cu inductors, wherein passivation serves as a diffusion barrier to protect Cu from corrosion. If the Cu inductor is formed below the last metal level (i.e. the last metal layer before the chip passivation layer), then planarization of subsequent metal levels is difficult and/or expensive. If the Cu inductor is formed at or above the last metal level, then passivation of the Cu is difficult. Typically, the last metal layer is passivated with Si3N4 and SiO2 layers, which are deposited by chemical vapor deposition (CVD), to prevent contaminants from diffusing into the transistors and wiring in the chip. However, the conformality of CVD films is not adequate to passivate thick Cu inductors. In addition, the processes used to form the inductor and the inductor passivation must not damage the bond pads.